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libmsr
0.3.0
A friendlier interface to accessing MSRs on Intel platforms
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libmsr
0.3.0
A friendlier interface to accessing MSRs on Intel platforms
|
Structure containing enabled/disabled platform-specific features as encoded in IA32_MISC_ENABLE. More...
#include <msr_misc.h>
Public Attributes | |
| uint64_t | raw |
| Raw 64-bit value stored in IA32_MISC_ENABLE. | |
| __u8 | fast_string_enable |
| Enable/disable fast string operations. | |
| __u8 | auto_TCC_enable |
| Enable/disable automatic thermal control circuit (TCC) and Thermal Monitor 1 (TM1) feature. | |
| __u8 | performance_monitoring |
| Performance monitoring is available or unavailable. | |
| __u8 | branch_trace_storage_unavail |
| Branch trace storage (BTS) is supported or unsupported. | |
| __u8 | precise_event_based_sampling_unavail |
| Processor event-based sampling (PEBS) is supported or unsupported. | |
| __u8 | TM2_enable |
| Enable/disable Thermal Monitor 2 (TM2). | |
| __u8 | enhanced_Intel_SpeedStep_Tech_enable |
| Enable/disable Enhanced Intel SpeedStep Technology. | |
| __u8 | enable_monitor_fsm |
| Enable/disable monitor FSM. | |
| __u8 | limit_CPUID_maxval |
| Limit CPUID maxval. | |
| __u8 | xTPR_message_disable |
| Enable/disable xTPR messages. | |
| __u8 | XD_bit_disable |
| Enable/disable Execute Disable Bit (XD bit) feature. | |
| __u8 | turbo_mode_disable |
| Enable/disable Intel Dynamic Acceleration (IDA). | |
Structure containing enabled/disabled platform-specific features as encoded in IA32_MISC_ENABLE.
| __u8 misc_enable::auto_TCC_enable |
Enable/disable automatic thermal control circuit (TCC) and Thermal Monitor 1 (TM1) feature.
Thermal Monitor 1 (TM1) controls the CPU temperature by modulating the duty cycle of the clock. If 1, the TCC portion of the Intel Thermal Monitor feature and TM1 are enabled, allowing the CPU to automatically reduce power consumption in response to TCC activation. If 0 (default), this feature is disabled. Disabling this feature may be ignored in critical thermal conditions. In this case, TM1, TM2, and adaptive thermal throttling will still be active. This bit field (bit 3) is R/W.
| __u8 misc_enable::branch_trace_storage_unavail |
Branch trace storage (BTS) is supported or unsupported.
The branch trace store (BTS) feature provides capability of saving branch records in a memory-resident BTS buffer. If 1, BTS is not supported by the platform, else it is supported. This bit field (bit 11) is RO and is thread-level scope.
| __u8 misc_enable::enable_monitor_fsm |
Enable/disable monitor FSM.
The MONITOR and MWAIT instructions help improve thread synchronization in multi-threaded environments. If 1 (default), MONITOR/MWAIT are supported. If 0, the MONITOR feature flag is not set, indicating that MONITOR/MWAIT are not supported by the platform. This bit field (bit 18) is R/W and is thread-level scope.
| __u8 misc_enable::enhanced_Intel_SpeedStep_Tech_enable |
Enable/disable Enhanced Intel SpeedStep Technology.
Intel SpeedStep Technology enables CPU power management with P-state transitions. If 1, Enhanced Intel SpeedStep Technology is enabled, else it is disabled. This bit field (bit 16) is R/W and is package-level scope.
| __u8 misc_enable::fast_string_enable |
Enable/disable fast string operations.
Fast string operations are string operations initiated with the MOVS/STOS instructions and the REP prefix. If 1 (default), stores within a single string operation may execute out of order. If 0, fast string operations are disabled. This bit field (bit 0) is R/W and is thread-level scope.
| __u8 misc_enable::limit_CPUID_maxval |
Limit CPUID maxval.
This feature only needs to be enabled if the OS does not support specific features. CPUID retrieves information about the platform, the higher the value, the more information that can be retrieved. Before setting this bit, the BIOS must execute the CPUID.0H and examine the max value returned in EAX[7:0]. If the max is greater than 3, this feature is supported, else it is not supported. This bit field (bit 22) is R/W and is thread-level scope.
| __u8 misc_enable::performance_monitoring |
Performance monitoring is available or unavailable.
If 1, performance monitoring is enabled, else it is disabled. This bit field (bit 7) if RO and is thread-level scope.
| __u8 misc_enable::precise_event_based_sampling_unavail |
Processor event-based sampling (PEBS) is supported or unsupported.
Processor event-based sampling (PEBS) uses an interrupt to store a set of architectural state information for the platform. If 1, PEBS is not supported by the platform, else it is supported. This bit field (bit 12) is RO and is thread-level scope.
| uint64_t misc_enable::raw |
Raw 64-bit value stored in IA32_MISC_ENABLE.
| __u8 misc_enable::TM2_enable |
Enable/disable Thermal Monitor 2 (TM2).
Thermal Monitor 2 (TM2) is an additional thermal protection feature to Thermal Monitor 1 (TM1). If TM2 encounters the CPU temperature rising above some threshold, it reduces the CPU frequency and voltage, while degrading performance less than TM1. If 1 and the thermal sensor indicates the CPU temperature has reached the pre-defined threshold, the TM2 feature is engaged. If 0, then TM2 has not been activated. This bit field (bit 13) is R/W.
| __u8 misc_enable::turbo_mode_disable |
Enable/disable Intel Dynamic Acceleration (IDA).
Intel Dynamic Acceleration (IDA) leverages thermal headroom to allow a single core to run at a higher frequency when the OS demands increased performance. If 1 on platforms supporting IDA, the feature is disabled. If 0 on platforms supporting IDA, then the feature is enabled. The power on default value is used by the BIOS to detect hardware support of Turbo Boost mode. If power-on default is 1, Turbo Boost is available on the platform, else it is not available. This bit field (bit 38) is R/W and is package-level scope.
| __u8 misc_enable::XD_bit_disable |
Enable/disable Execute Disable Bit (XD bit) feature.
The Execute Disable Bit (XD bit) controls page access restriction through instruction fetches from PAE pages. If 1, the XD bit feature is disabled. If 0 (default), the feature (if available) allows the OS to enable PAE paging, leveraging data only pages. This bit field (bit 34) is R/W and is thread-level scope.
| __u8 misc_enable::xTPR_message_disable |
Enable/disable xTPR messages.
xTPR messages are optional messages enabling the process to inform the chipset of its priority. If 1, xTPR messages are disabled. This bit field (bit 23) is R/W and is thread-level scope.
1.8.2
