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A friendlier interface to accessing MSRs on Intel platforms
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msr_rapl.h
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1 /* msr_rapl.h
2  *
3  * Copyright (c) 2011-2016, Lawrence Livermore National Security, LLC.
4  * LLNL-CODE-645430
5  *
6  * Produced at Lawrence Livermore National Laboratory
7  * Written by Barry Rountree, rountree@llnl.gov
8  * Scott Walker, walker91@llnl.gov
9  * Kathleen Shoga, shoga1@llnl.gov
10  *
11  * All rights reserved.
12  *
13  * This file is part of libmsr.
14  *
15  * libmsr is free software: you can redistribute it and/or modify it under the
16  * terms of the GNU Lesser General Public License as published by the Free
17  * Software Foundation, either version 3 of the License, or (at your option)
18  * any later version.
19  *
20  * libmsr is distributed in the hope that it will be useful, but WITHOUT ANY
21  * WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
22  * FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
23  * details.
24  *
25  * You should have received a copy of the GNU Lesser General Public License
26  * along with libmsr. If not, see <http://www.gnu.org/licenses/>.
27  *
28  * This material is based upon work supported by the U.S. Department of
29  * Energy's Lawrence Livermore National Laboratory. Office of Science, under
30  * Award number DE-AC52-07NA27344.
31  *
32  */
33 
34 #ifndef MSR_RAPL_H_INCLUDE
35 #define MSR_RAPL_H_INCLUDE
36 
37 #include <stdint.h>
38 #include <stdio.h>
39 #include <sys/time.h>
40 
41 #include "master.h"
42 
43 #ifdef __cplusplus
44 extern "C" {
45 #endif
46 
47 // Processor specific rapl flags (see rapl_init function)
48 // These indicate which rapl MSRs are available for a given cpu model
49 // bit: address, register
50 // 0: 606h, MSR_RAPL_POWER_UNIT
51 // 1: 610h, MSR_PKG_POWER_LIMIT
52 // 2: 611h, MSR_PKG_ENERGY_STATUS
53 // 3: 613h, MSR_PKG_PERF_STATUS
54 // 4: 614h, MSR_PKG_POWER_INFO
55 // 5: 618h, MSR_DRAM_POWER_LIMIT
56 // 6: 619h, MSR_DRAM_ENERGY_STATUS
57 // 7: 61Bi, MSR_DRAM_PERF_STATUS
58 // 8: 61Ch, MSR_DRAM_POWER_INFO
59 // 9: 638h, MSR_PP0_POWER_LIMIT
60 // 10: 639h, MSR_PP0_ENERGY_STATUS
61 // 11: 63Ah, MSR_PP0_POLICY
62 // 12: 63Bh, MSR_PP0_PERF_STATUS
63 // 13: 640h, MSR_PP1_POWER_LIMIT
64 // 14: 641h, MSR_PP1_ENERGY_STATUS
65 // 15: 642h, MSR_PP1_POLICY
66 // 16: 64Ch, MSR_TURBO_ACTIVATION_RATIO
67 // 17: 66Eh, MSR_PKG_POWER_INFO
68 // 18: 690h, MSR_CORE_PERF_LIMIT_REASONS
69 // 19: 6B0h, MSR_GRAPHICS_PERF_LIMIT_REASONS
70 // 20: 6B1h, MSR_RING_PERF_LIMIT_REASONS
71 // 21: 1ADh, MSR_TURBO_RATIO_LIMIT
72 // 22: 1AEh, MSR_TURBO_RATIO_LIMIT1
73 #define MF_06_37 (0x407)
74 #define MF_06_4A (0x407)
75 #define MF_06_5A (0x407)
76 #define MF_06_4D (0x20003)
77 #define MF_06_4C (0x607)
78 #define MF_06_2A (0xFE17) // Sandy Bridge
79 #define MF_06_2D (0x7FF) // Sandy Bridge
80 #define MF_06_3A (0xFE17)
81 #define MF_06_3E (0x6007F7) // Ivy Bridge
82 #define MF_06_3C (0x1CEE17) // disabled pp0_perf_status, not on this architecture
83 #define MF_06_45 (0x1CFE17)
84 #define MF_06_46 (0x1CFE17)
85 #define MF_06_3F (0x1C01FF) // disabled PP registers, not on this architecture
86 #define MF_06_3D (0x1CFE17)
87 #define MF_06_47 (0x1CFE17)
88 #define MF_06_4F (0x1CFE17)
89 #define MF_06_56 (0x1CFE17)
90 #define MF_06_4E (0x1EFE17)
91 #define MF_06_5E (0x1EFE17)
92 #define MF_06_57 (0x507FF)
93 
94 // Register flags
95 // These are used to check against the rapl flags (see above) to see if a
96 // register exists
97 #define POWER_UNIT (0x1L)
98 #define PKG_POWER_LIMIT (0x2L)
99 #define PKG_ENERGY_STATUS (0x4L)
100 #define PKG_PERF_STATUS (0x8L)
101 #define PKG_POWER_INFO (0x10L)
102 #define DRAM_POWER_LIMIT (0x20L)
103 #define DRAM_ENERGY_STATUS (0x40L)
104 #define DRAM_PERF_STATUS (0x80L)
105 #define DRAM_POWER_INFO (0x100L)
106 #define PP0_POWER_LIMIT (0x200L)
107 #define PP0_ENERGY_STATUS (0x400L)
108 #define PP0_POLICY (0x800L)
109 #define PP0_PERF_STATUS (0x1000L)
110 #define PP1_POWER_LIMIT (0x2000L)
111 #define PP1_ENERGY_STATUS (0x4000L)
112 #define PP1_POLICY (0x8000L)
113 #define TURBO_ACTIVATION_RATIO (0x10000L)
114 #define TURBO_RATIO_LIMIT (0x200000L)
115 #define TURBO_RATIO_LIMIT1 (0x400000L)
116 
117 
118 #define UINT_MAX 4294967295U // taken from limits.h
119 #define STD_ENERGY_UNIT 65536.0
120 
142 };
143 
146 struct rapl_units {
151  double joules;
154  double seconds;
157  double watts;
158 };
159 
162 struct rapl_data {
163  /**********/
164  /* Timers */
165  /**********/
167  struct timeval now;
169  struct timeval old_now;
171  double elapsed;
172 
173  /**************************/
174  /* RAPL Power Domain: PKG */
175  /**************************/
177  uint64_t **pkg_bits;
179  uint64_t *old_pkg_bits;
181  double *pkg_joules;
183  double *old_pkg_joules;
190  double *pkg_watts;
194  uint64_t **pkg_perf_count;
195 
196  /***************************/
197  /* RAPL Power Domain: DRAM */
198  /***************************/
200  uint64_t **dram_bits;
202  uint64_t *old_dram_bits;
204  double *dram_joules;
211  double *dram_watts;
215  uint64_t **dram_perf_count;
216 
217  /************************************/
218  /* RAPL Power Domain: Power Plane 0 */
219  /* (PP0, IA Processor Cores) */
220  /************************************/
222  uint64_t **pp0_bits;
224  uint64_t *old_pp0_bits;
226  double *pp0_joules;
228  double *old_pp0_joules;
233  double *pp0_watts;
237  uint64_t **pp0_perf_count;
240  uint64_t **pp0_policy;
241 
242  /************************************/
243  /* RAPL Power Domain: Power Plane 1 */
244  /* (PP1, Uncore Graphic Device) */
245  /************************************/
247  uint64_t **pp1_bits;
249  uint64_t *old_pp1_bits;
251  double *pp1_joules;
253  double *old_pp1_joules;
258  double *pp1_watts;
261  uint64_t **pp1_policy;
262 };
263 
265 struct rapl_limit {
267  uint64_t bits;
269  double watts;
271  double seconds;
272 };
273 
277  /**************************/
278  /* RAPL Power Domain: PKG */
279  /**************************/
293 
294  /***************************/
295  /* RAPL Power Domain: DRAM */
296  /***************************/
310 };
311 
324 int rapl_storage(struct rapl_data **data,
325  uint64_t **flags);
326 
330 int print_available_rapl(void);
331 
343 int rapl_init(struct rapl_data **rapl,
344  uint64_t **rapl_flags);
345 
362 int set_pkg_rapl_limit(const unsigned socket,
363  struct rapl_limit *limit1,
364  struct rapl_limit *limit2);
365 
380 int set_dram_rapl_limit(const unsigned socket,
381  struct rapl_limit *limit);
382 
399 int set_pp_rapl_limit(const unsigned socket,
400  struct rapl_limit *limit0,
401  struct rapl_limit *limit1);
402 
414 int get_rapl_power_info(const unsigned socket,
415  struct rapl_power_info *info);
416 
432 int set_pp_rapl_policies(const unsigned socket,
433  uint64_t *pp0,
434  uint64_t *pp1);
435 
445 int get_pp_rapl_policies(const unsigned socket,
446  uint64_t *pp0,
447  uint64_t *pp1);
448 
462 int get_pkg_rapl_limit(const unsigned socket,
463  struct rapl_limit *limit1,
464  struct rapl_limit *limit2);
465 
477 int get_dram_rapl_limit(const unsigned socket,
478  struct rapl_limit *limit);
479 
493 int get_pp_rapl_limit(const unsigned socket,
494  struct rapl_limit *limit0,
495  struct rapl_limit *limit1);
496 
502 void dump_rapl_limit(struct rapl_limit *L,
503  FILE *writedest);
504 
510 int dump_rapl_data_terse_label(FILE *writedest);
511 
517 int dump_rapl_data_terse(FILE *writedest);
518 
524 int dump_rapl_data(FILE *writedest);
525 
531 int dump_rapl_power_info(FILE *writedest);
532 
541 int poll_rapl_data(void);
542 
547 int delta_rapl_data(void);
548 
552 int read_rapl_data(void);
553 
557 void get_rapl_power_unit(struct rapl_units *ru);
558 
564 void dump_rapl_power_unit(FILE *writedest);
565 
566 #ifdef __cplusplus
567 }
568 #endif
569 #endif